The invention relates to a nonvolatile semiconductor memory having memory cells, such as a ferroelectric memory.
Nonvolatile semiconductor memories such as a ferroelectric memory and a flash memory exhibit unstable behaviors and can write erroneous data or often fails to write data when the supply voltage to the memory lowers below a certain limit, due to consumption of the cell for example. In order to prevent such anomaly, these memories are provided with a detection circuit for detecting the level of the supply voltage and disenabling the memories when the level is below a predetermined voltage.
For example, a detection circuit 50 as shown in FIG. 1(a) monitors the voltage at node P where the voltage is equal to a supply voltage Vcc multiplied by a ratio R2/(R1+R2). When the supply voltage Vcc lowers below the predetermined level, the detection circuit 50 sends a control signal to memory cells 51 and a logic circuit 52 via dotted signal lines as shown in FIG. 1(a). Upon receipt of the control signal, the memory cells 51 and the logic circuit 52 are disenabled. Such disenablement is called low-voltage lockout, and the predetermined level, lockout voltage.
In order to secure operational reliability of a nonvolatile semiconductor memory, the lockout voltage is set at a higher level B above the lowest operable voltage A, leaving a certain margin B-A above the voltage A as shown in FIG. 1(b). Thus, the allowable voltage range for the memory is the range B-C between the level B and the normal supply voltage C. Therefore, as seen from FIG. 1(b), range A-C is the maximum operable range, range O-A is the inoperable range, range O-B is the lockout range in which the memory cells 51 or the logic circuit 52 are not provided with the supply voltage.
In order to reduce the failure rate of nonvolatile memories during the working life, they are screened under harsh conditions such as a severe thermal stress, to thereby remove defective products. FIG. 2 is a graphical representation of a failure rate h(t) as a function of time for a semiconductor memory, in which region O-D is an initial error-liable period where most defects can be found in screening, period D-E is the use period (i.e. period that the memory can be used reliably and can be put on market). Point E is the end of the life of a memory. Unlike flash memories which manifest defects at an early stage of such screening if they are defective, ferroelectric memories are likely to manifest defects throughout their working life period, as shown in FIG. 2.
Therefore, in order to perform sufficient screening of products to a degree that the products are reliable throughout their working lives, it must be performed over a very long period of time, which, however, disadvantageously shorten their working lives and reduce the overall reliability of a device that uses the over-tested memories.
However, a quicker screening can be done, especially for ferroelectric memories, by lowering the screening voltage, since operating conditions for ferroelectric memories become severer at a lower operating voltage. It is noted in FIG. 2 that if screening can be attained up to point F in the working period by lowering the screening voltage below a normal screening voltage (5 Volts for example), one may virtually attain full screening, or the screening over the entire working life up to point E, by performing the screening at a level (3 Volts for example) which is exceedingly lower than the normal screening voltage.
However, as mentioned above, in order to ensure stable operation of a semiconductor memory like a ferroelectric memory and a flash memory, the low-voltage lockout mechanism will be activated when the supply voltage lowers below the lockout voltage, although the supply voltage is still within the allowable operable range B-C. Hence, because of this fixed lockout voltage, the screening voltage cannot be dropped below level B, the lower limit of the operative range B-C. Therefore, sufficient screening is prohibited. On the other hand, it is not recommended to reduce the lower limit B itself of the nominal operative range, since then a chance of erroneous memory write will increase during the working life, and the reliability of the memory will not be guaranteed.
The invention is directed to an improvement in a semiconductor memory, wherein the semiconductor memory can be tested for screening at a lower screening voltage than the preset lockout voltage of a low-voltage lockout mechanism thereof.
In one aspect of the invention, a nonvolatile semiconductor memory includes:
a supply voltage terminal for receiving a supply voltage from an external source;
a multiplicity of memory cells;
voltage selection means coupled to the terminal for selectively outputting a first and a second voltage to be supplied to the memory cells; and
voltage dropping means coupled between the voltage selection means and the memory cells for dropping the second voltage output from the voltage selection means before it is input to the memory cells.
The voltage selection means is controllable by an external control signal. The voltage selection means may provide the first and the second output voltages via a p-channel MOS transistor (referred to as PMOS transistor) and an n-channel MOS transistor (referred to as NMOS transistor), respectively, and may generate a control voltage for controlling the PMOS and NMOS transistors. Also, the voltage dropping means may comprise one NMOS transistor/diode or a multiplicity of NMOS transistors/diodes connected in series.
In another aspect of the invention, a nonvolatile semiconductor memory includes:
a supply voltage terminal for receiving a supply voltage;
a multiplicity of memory cells;
voltage dropping means coupled to the terminal for dropping the supply voltage to a predetermined voltage; and
voltage selection means coupled to the voltage dropping means and the terminal for selecting either the predetermined voltage or the supply voltage to be provided to the memory cells.
The voltage selection means may be controlled by an external control signal. The voltage selection means is adapted to selectively output the predetermined or the supply voltages via an NMOS transistor and a PMOS transistor, respectively, and generates a control voltage for controlling the transistors.
The voltage dropping means may comprise one NMOS transistor/diode or a multiplicity of NMOS transistors/diodes connected in series.
In this arrangement, a nonvolatile semiconductor memory of the invention may provide on one hand the supply voltage to memory controlling means such as logic circuits and an address control circuit, and provide on the other hand either the supply voltage or a dropped voltage derived therefrom to the memory cells. Accordingly, if a nonvolatile semiconductor memory has a low-voltage lockout mechanism, screening can be safely performed at a lower screening voltage than the lockout voltage.
This arrangement, therefore, permits quick and effective screening of a nonvolatile memory at a low voltage, which is also preferable for damage-free screening.
It is noted that the selection means is constructed using a PMOS and an NMOS transistors which can be switched on and off by an external control signal, thereby allowing easy selection of the screening voltage.
It is also noted that the voltage dropping means consists of an NMOS transistor or a multiplicity of NMOS transistors connected in series, which causes the supplied voltage to be dropped easily to a required level in cooperation with the NMOS transistor of the selection means.
In addition, a nonvolatile semiconductor memory of the invention may be operated at a lower voltage than its nominal operating voltage during the working life period, if desired, by simply switching the operating conditions of the selection means. That is, one may selectively apply a lower voltage to memory cells only but not to other elements. This helps protect the memory cells and extend the working life of the memory.
In a further aspect of the invention, a nonvolatile semiconductor memory includes:
at least one memory cell;
an internal voltage controller coupled to at least one voltage controller transistor wherein the internal voltage controller controls the at least one voltage controller transistor for selectively outputting a voltage to be supplied to the at least one memory cell; and
at least two series-connected transistors coupled between the at least one voltage controller transistor and the at least one memory cell for dropping the voltage output from the at least one voltage controller transistor before it is input to the at least one memory cell.
The internal voltage controller may be controlled by an external control signal. The at least one voltage controller transistor may include at least one p-channel transistor and at least one n-channel transistor. Also, the internal voltage controller may generate a control voltage for controlling the at least one voltage controller transistor. In addition, the at least two series-connected transistors may include n-channel transistors.
In a further aspect of the invention, a nonvolatile semiconductor memory includes:
a supply voltage terminal for receiving a supply voltage;
at least one memory cell;
at least two series-connected transistors for dropping the supply voltage before it is input to the at least one memory cell, the at least two series-connected transistors coupled between the supply voltage terminal and the at least one memory cell; and
at least one voltage controller transistor wherein each of the at least one voltage controller transistor is coupled between an internal voltage controller and one of the supply voltage terminal and the at least two series-connected transistors, wherein the internal voltage controller controls the at least one voltage controller transistor for selectively outputting a voltage to be supplied to the at least one memory cell.
As in the prior aspect of the invention, the internal voltage controller may be controlled by an external control signal. The at least one voltage controller transistor may include at least one p-channel transistor and at least one n-channel transistor. Also, the internal voltage controller may generate a control voltage for controlling the at least one voltage controller transistor. In addition, the at least two series-connected transistors may include n-channel transistors.xe2x80x9d